1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of the Related Art
As disclosed in JP2007-311385A, JP2004-363573A and JP2008-251964A, efforts are being made to develop a semiconductor device in which a plurality of semiconductor chips is stacked through through-hole electrodes, in order to cope with the miniaturization of electronic apparatus equipped with semiconductor chips. In such a semiconductor device, connecting terminals need to be disposed respectively at one and the other ends of each through-hole electrode to form a strong junction therebetween and fix the through-hole electrodes to one another, in order to stack a plurality of semiconductor chips.
FIGS. 13 to 16 are schematic cross-sectional views used to explain a method for manufacturing a related semiconductor device. Hereinafter, a description will be given by defining a surface in which semiconductor elements are formed as a front surface, and defining a surface opposite to the front surface as a rear surface, in a semiconductor substrate (wafer). In FIG. 13 to FIG. 16, only one through-hole electrode is shown for purposes of illustration. In addition, a part from the rear surface side of the semiconductor substrate to first interconnect layer 53 in the through-hole electrode is omitted from the figures.
First, as illustrated in FIG. 13, interlayer insulating film 52, first interconnect layer 53, and second interconnect layer 55 are formed on and above the front surface of semiconductor substrate 51. This interlayer insulating film 52 is formed of silicon dioxide (SiO2) or the like. A connection is made between first interconnect layer 53 and second interconnect layer 55 by contact plug 54.
In FIG. 13, trench 64 is formed so as to surround the through-hole electrode provided in semiconductor substrate 51. An insulator, such as silicon dioxide or the like, is filled inside trench 64. This trench 64 prevents through-hole electrodes disposed in abutment with each other from short-circuiting to each other. In addition, trench 64 is previously formed on the front surface side of semiconductor substrate 51 prior to a step of forming semiconductor elements. Trench 64 need not necessarily penetrate to the rear surface of the semiconductor substrate.
Reference numeral 56 denotes a protective film formed of polyimide or the like and an opening is created therein, so as to expose part of the upper surface of second interconnect layer 55. Reference numeral 57 denotes a metal seed film provided so as to cover the upper surface of protective film 56. Metal seed film 57 is provided in order to form a projecting electrode (bump) using an electrolytic plating method. Metal seed film 57 is in contact with an exposed surface of second interconnect layer 55. Metal seed film 57 is formed using a laminated film (film thickness: approximately 700 nm) in which a titanium (Ti) film and a copper (Cu) film are successively laminated. Reference numeral 58 denotes a resist film (film thickness: 15 to 20 μm) including an opening in a position thereof where the projecting electrode is to be formed.
Next, as illustrated in FIG. 14, projecting electrode 59 made of copper is formed in the opening not covered with resist film 58 to a thickness of approximately 10 μm using an electrolytic plating method. Sn—Ag alloy film 60 made of tin (Sn) and silver (Ag) is formed on the upper surface of projecting electrode 59 to a thickness of 2 to 3 μm using an electrolytic plating method. After that, resist film 58 is removed, and then metal seed film 57 is removed using a chemical solution containing sulfuric acid (H2SO4) and nitric acid (HNO3). A titanium film in which metal seed film 57 remains is removed using a chemical solution containing potassium hydroxide (KOH).
Side surfaces of projecting electrode 59 made of copper are also removed partially by etching at the time of removing this metal seed film 57, but Sn—Ag alloy film 60 is not etched. There is therefore formed an overhanging shape in which Sn—Ag alloy film 60 protrudes over an outer circumference of projecting electrode 59.
Next, as illustrated in FIG. 15, supporting substrate (support plate) 62 is bonded onto the front surface side of semiconductor substrate 51 through a adhesion layer 61. As supporting substrate 62, a transparent glass substrate or a hard resin substrate can be used. After this, the rear surface side of semiconductor substrate 51 is polished (back-grind) until a predetermined thickness is reached, thereby thinning the substrate and exposing the edges of previously-formed trench 64.
After this, a metal plug (not illustrated) made of copper is formed from the rear surface side of the semiconductor substrate, so as to connect to first interconnect layer 53. A thin-film plating layer made of gold (Au) is provided in an exposed part of the metal plug. After the formation of the metal plug, supporting substrate 62 is removed.
Supporting substrate 62 is removed by previously irradiating ultraviolet light from the front surface side and thereby reducing the fixing strength of adhesion layer 61.
As illustrated in FIG. 16, the other process may be used. In this process, an Sn—Ag alloy film may be formed on projecting electrode 59 on the front surface side. Then, this film may be completely reflowed at a temperature of approximately 250 to 300° C. Reflowed Sn—Ag alloy film 60a is reshaped into a dome-like shape due to surface tension, and the overhanging shape is thus eliminated. This process prevents projecting electrode 59 from being pulled by supporting substrate 62 and dropping off, due to an overhanging shape at the time of removing supporting substrate 62.